1. Field of the Invention
This invention relates to frequency synthesizers and in particular to an all-digital frequency synthesizer and especially to techniques used to create a lower frequency clock from a high frequency clock.
2. Description of Related Art
It is well known in the art that a multiple number of frequencies can be generated from a single source. These techniques may be either analog or digital and may have output signals that are either analog sine waves or purely digital pulse trains.
A typical application for a frequency synthesizer is a phase locked loop. In a phase locked loop the output of frequency synthesizer is compared to a reference signal. An error signal that represents the difference in the phase and frequency of the output of the frequency synthesizer and the reference signal are used to vary the frequency of the frequency synthesizer. The error signal is passed through a loop filter to eliminate any response to unwanted transient signals. As the error signal approaches zero, the phase locked loop is said to be locked.
A digital phase locked loop originally contained a binary reference signal and a binary output signal with an analog frequency synthesizer, loop filter and comparator. As digital circuits have improved in performance, the components may now be implemented in digital circuitry or a software program on a microcomputer.
FIG. 1 shows a block diagram of an all digital phase locked loop as described in Phase Locked Loops: Theory, Design, and Application by Best, McGraw-Hill Inc. 1993. The phase detector compares the output u.sub.2 of the digital control oscillator DCO with the digital reference signal u.sub.1. The output of the phase detector is connected to the DN/UP input of the counter, which forms the loop filter. The K clock is an input to the K counter that is frequency that is a frequency that is a factor M times the desired output frequency F.sub.o of the digital controlled oscillator DCO. The K Modulus Control sets the number at which the K counter will have carry signal.
The DN/UP input to the K counter causes the K counter to count up to the value of the K Modulus if the DN/UP input has a level to activate the up counting. The DN/UP input causes the K counter to count down to zero if the DN/UP input has a level to activate the down counting. If the K counter exceeds the value of the K Modulus, the carry output is activated. If the K counter is decremented to less than zero, the borrow output is activated.
If the signals u.sub.1 and u.sub.2 are of identical frequency and phase, the output of the phase detector will be a square wave. This will cause the K counter to count up for the first level of the square wave and to count down for the second level of the square wave. As long as the DN/UP input signal is a balance square wave, neither the carry or the borrow outputs will be triggered. If the signals u.sub.1 and u.sub.2 become out of phase and of unequal frequency, the period of the signal at the DN/UP input will not have equal period at the first level versus the second level and there will eventually be either a carry or a borrow signal.
The digital control oscillator DCO has and increment/decrement counter (ID counter). The ID clock input of the ID counter is a frequency that is a fraction of two times a factor N times the frequency F.sub.o of the output signal u.sub.2. The output ID.sub.out will be a frequency that is one half of the input ID clock.
The carry output of the Loop Filter is connected to the increment input INC of the ID counter and the borrow output of the Loop Filter is connected to the decrement input DEC of the ID counter. If the carry signal is activated, a single pulse is added to the ID counter output signal ID.sub.out and conversely if the borrow signal is activated, a single pulse is subtracted from the ID counter output ID.sub.out.
The ID counter output ID.sub.out is connected tot he input CP of the .div.N counter. The N control determines the factor of N that the input CP is divided by to form the frequency F.sub.o of the output u.sub.2.
The variance of the phase and frequency of the output u.sub.2 from the desired frequency is called jitter. As the phase detector compares the reference signal u.sub.1 to the output signal u.sub.2, any difference in frequency will be a function of the weighted number of carry pulses from the K counter versus the number of borrow pulses. The size of the error maybe on the order of the pulse width of the two signals u.sub.1 and u.sub.2. Also the time required to become totally locked to a new reference frequency u.sub.1 will be a function of the frequency of the K clock and again maybe as long as the pulse width of the reference signal u.sub.1 and the output signal u.sub.2.
U.S. Pat. No. 5,430,764 (Chren, Jr.) describes a frequency synthesizer using a residue number system to generate an address to find a value in a look-up table containing the digital values of a sine wave. These values are presented to a digital-to-analog converter to create an analog sine wave output.
U.S. Pat. No. 5,467,294 (Hsu, et al.) illustrates an apparatus for the programmable generation of sine waves. The digital values to describe the sine wave are maintained in a ROM lookup table.
U.S. Pat. No. 4,746,870 (Underhill) describes a frequency synthesizer with reduced jitter. The frequency synthesizer has a reference frequency source, a frequency reduction means, and a jitter compensation signal circuit. The frequency reduction means cancels pulses from a frequency to be reduced. The jitter compensation signal circuit is arranged to compensate for any jitter in the output frequency that would otherwise be caused by each cancelled cycle. The jitter compensation signal is derived from a jitter-containing pulse train via a D.C. removal circuit and an integrator. Additionally, a perturbation signal is injected by a control device which causes pulses to be added to and also to be subtracted, by a pulse addition and a "pulse swallowing" circuit respectively, from the frequency to be reduced. The jitter caused by this addition and subtraction also being compensated for by the compensation signal circuit.
U.S. Pat. No. 5,187,722 (Petty) teaches a frequency synthesis circuit which provides an output frequency that greater than a fractional multiple of a reference signal frequency. The frequency synthesis circuit utilizes a fraction multiplier that is placed in the feedback path of a phase locked loop. The fractional multiplication provided is equal to the ratio of the reference signal frequency the desired frequency. The circuit can be utilized in either analog or digitally implemented phase-locked loops and can be coupled with the use a fractional multiplier in the feedforward path of the digitally implemented phase locked loop to improve jitter performance.
U.S. Pat. No. 5,276,408 (Norimatsu) discloses a phase locked loop frequency synthesizer that can modify output frequency at high speed. The frequency synthesizer has, a first pulse removing circuit connected between a reference signal generator and a phase-frequency comparator. A second pulse removing circuit is connected between a variable frequency divider and the phase-frequency comparator. Upon receiving of a first removing data indicative of a first pulse number, the first pulse removing circuit removes pulses from the reference signal that are equal in number to the first pulse number for a first predetermined cycle to produce a first pulse removed signal. Upon receiving of a second removing data indicative of a second pulse number, the second pulse removing circuit removes pulses from the divided signal that are equal in number to the second pulse number for a second predetermined cycle to produce a second pulse removed signal. The current controlling circuit controls current supplied from/to a charge pump circuit after receiving a current command. A control circuit is connected between the phase-frequency comparator and the charge pump circuit. A switch is inserted between the loop filter and the voltage controlled oscillator. When the switch switches off a PLL, a DIA converter supplies a control voltage to the voltage controlled oscillator and a filter capacitor of the loop filter. The charge pump circuit comprises a control circuit, a constant current circuit, an integrating circuit, and a sample and hold circuit.